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- 40GBase-R or 100GBase-R PCS solution compliant with IEEE802.3ba Specification Draft
- Multi-Lane Distribution (MLD) across 4 or 20 Virtual Lanes for 40 Gigabit or 100 Gigabit, respectively
- Periodic Alignment Marker insertion / striping - Flexible Serdes Interfaces supporting 16/20/32/40 bit
Interface Options:
- 100G: CGMII (192bit for ASIC, 384bit for FPGA)
- 40G: XLGMII (192bit)
- CAUI (16..40bit Serdes)
Target Technologies:
- FPGA
- Altera Stratix IV
ASIC
- FPGA: Altera Stratix IV
- ASIC: 0.09um and below standard cell ASIC
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| Product Brief PDF |
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