MorethanIP QSGMII PCS Core implements 8B/10B coding, link synchronization, frame encapsulation generation / termination compliant with Clause 36 of the IEEE802.3 standard and adapted to the Cisco QSMII specification version 1.2.

- Compliant with Cisco QSGMII specification version 1.2
  and implements four 10/100/1000 links

- Implements QSGMII Auto-Negotiation
  (Cisco Specification) for Port 0
  and SGMII Auto-Negotiation (Cisco Specification)
  for all other ports.

- Implements QSGMII K28.5 swapper on port 0 transmit
   and K28.1 swapper on Port 0 receive to support
   four MII / GMII ports

- Programmable Decoder running disparity checking disable

- Seamless interface to commercial or embedded
   SERDES via a standard 40-Bit interface