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| News 2005 | ||
Karlsfeld December 21, 2005 MorethanIP, announces several new cores for the Ethernet application space for proprietary 2.5 Gbps Ethernet and an improved Ethernet Switch Core with quality of service support. A new XAUI/SPI4.2 reference design helps to bridge network processors with SPI4.2 system interface to 10G Ethernet lines and HiGig Switches and Backplanes using the XAUI module interface. Karlsfeld June 28, 2005 MorethanIP, Altera and InterNiche today announced the availability of a networking reference design for Altera’s Nios® II embedded processor. Delivering over 60 Mbits of throughput via TCP/IP over a 100-Mbit link, embedded designers can leverage the flexibility, performance and ease-of-use of the reference design for embedded applications requiring high-throughput network connectivity. View complete press release Karlsfeld June 20, 2005 MorethanIP releases new 10 Gigabit Ethernet Base-X PCS Core for XGXS/XAUI implementations. The 10G Base-X or XGXS (10 Gigabit Extension Sub-Layer) PCS (Physical Coding Sub-Layer) Core is designed to comply with the IEEE802.3ae Clause 48 and can be used, together with MorethanIP 10 Gigabit Ethernet MAC Core, to implement a 10 Gigabit Ethernet solution with a XAUI. Karlsfeld June 17, 2005 MorethanIP's Ethernet MAC Core with TCP/IP Protocol Acceleration (MAC-NET Core) showing highest performance with various embedded networking protocol stack solutions. In cooperation with Interniche, a specialist provider of internet protocol software stacks and networking expertise, a Nios-II Network Acceleration Reference Design is now available, illustrating how to achieve high bandwidth network connectivity in a Nios® II soft-core processor based system. The Reference Design and a white paper with further information is available for download from the Altera Reference Design Pages. Karlsfeld June 17, 2005 MorethanIP releases a new Ethernet 10/100/1000 Ethernet PHY daughter board hardware utilizing the Marvell 88E1111 low power triple-speed PHY device to provide designers with a flexible Ethernet development environment in conjunction with various available FPGA development boards. Karlsfeld June 17, 2005 MorethanIP releases a new 10 Gigabit Ethernet HiGig MAC Core for high performance switching applications. The HiGig Protocol provides a standard mechanism to interconnect switches for a single system defining an efficient way to forward Frames for Unicast, Broadcast, Multicast (Layer 2 and IP) and Control Traffic. The HiGig Protocol implements HiGig Frames, which are formed by tagging standard Ethernet frames with a specific HiGig header. Karlsfeld June 16, 2005 MorethanIP releases a new Gigabit Ethernet SGMII PCS Core for 10/100/1000 Ethernet Applications implementing the low pin-count serial gigabit media independent interface (SGMII). Karlsfeld March 5, 2005 |
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