200G/400G Ethernet IP
In the continuous development of the IEEE for Ethernet lays the foundation for highly scalable and yet well defined networking infrastructures adopted by many industries. One of the major achievements is Ethernet’s scalability in supporting applications from low rate consumer and home environments to the highest performance telecom backbone and storage networks. This flexibility however calls for the system architect to choose the right compromise between integration complexity, application support, scalability, new standards support and, eventually, time and risk for product development. MorethanIP provides Cores for each Ethernet speed from 10Mbps to 400Gbps and above.
The 400 Gigabit Ethernet Base-R PCS Core is compliant with the IEEE 802.3bs standard.
The Core implements the Reed-Solomon FEC (RS-FEC) of IEEE 802.3bs Clause 119 using RS(544/514) codewords. The RS-FEC sublayer performs 257b transcoding and distributes data across 8 (200G) or 16 (400G) virtual FEC lanes which are bit-multiplexed to the Serdes lanes.
On receive it re-aligns the serial data stream to the RS-FEC codeword boundaries performs deskew and lane re-mapping and performs RS-FEC error correction and decode.
On the line side, the Core supports 16x26Gbps, 8x53Gbps or 4x106Gbps Serdes interface options for 400G and 8 or 4 or 2 lanes for 200G respectively.
On the application side, the Core implements a 512-Bit CDMII (400G Media Independent Interface) with dynamic support for 200G and 400G rates.
- 400G Base-R PCS layer implementing IEEE P802.3bs specification
- Transmit and Receive data-path operating on a single Reference clock with a low minimum Frequency requirement of 800MHz
- Standard 512bit CDMII MAC Interface
- Reed-Solomon Forward Error Correction RS-FEC(544, 514)
- Low Latency implementation with dedicated wide RS-FEC Datapath
- Configurable FEC symbol error monitoring with High-Symbol error indication (Hi-SER)
- Additional FEC symbol error monitoring with Degrade indication (Deg-SER)
- Transport of degrade indications through marker block dedicated signaling bits
- The RS-FEC error propagation to the PCS can be bypassed with software programming to reduce the Core latency.
- Flexible Serdes interfaces configurable to implement 26.5625 or 53.125Gbps or 106.25Gbps interfaces
- Control/Configuration/Status register access with 16-bit generic control interface.
The 400 Gigabit Ethernet MAC Core is designed to comply with the 400G Ethernet IEEE 802.3bs Specification.
The MAC can be used in transport or Ethernet switching applications, passing received MAC frames without modification to the User application or to the Ethernet line. It provides support statistics for IEEE managed objects, IETF MIB-II and RMON for management applications (e.g. SNMP).
On the application side, the MAC Core implements a flexible FIFO interface that can be connected to a custom user application supporting 200G or flexible 200G/400G rates.
On the Ethernet line side, the Core implements a 512bit wide CDMII (400G Media Independent Interface) for direct interfacing to a 200G or 400G PCS layer.
- Full MAC layer and Reconciliation sub-layer implementation compliant with IEEE 802.3bs specifications for 200G and 400G Ethernet.
- 512bit application FIFO interface for 200G only operation.
- 1024bit application FIFO interface for 200G/400G operation.
- Line side 512bit CDMII to 200G/400G PCS.
- CRC-32 checking with optional forwarding of the FCS field to the user application
- CRC-32 generation and append on transmit or forwarding of user application provided FCS selectable on a per-frame basis
- Optional Ethernet Pause Frame (802.3 Annex 31A) termination providing fully automated flow control without any user application overhead
- Optional Priority Flow Control (PFC) frame support allowing 8 or 16 classes for higher layer congestion management
- Pause Frame generation by dedicated command pin with programmable Quanta
- Programmable frame maximum length providing support for any frame up to 32K (e.g. Jumbo Frame or any tagged Frame)
- Support for VLAN tagged frames according to IEEE 802.1Q
- Basic and mandatory managed Objects statistics and IETF Management Information Database (MIB) package (RFC2665) and Remote Network Monitoring (RMON) counters
- Optional internal statistics 64bit counters or statistics vector at toplevel for external statistics counting.
- Clause 45 MDIO Master interface for PHY device configuration and management.
- Support for IEEE 1588 applications providing frame timestamping.
- Optional Timing Frame update module with automatic on-the-fly (1-step) correction field update for IEEE 1588 applications.