800G Ethernet IP

Overview

The 800 Gigabit Ethernet Base-R PCS Core is following the 400G IEEE 802.3bs standardization and is designed to be used in conjunction with the MorethanIP 800 Gigabit Ethernet MAC Core to create flexible system solutions for 800 Gigabit Ethernet applications.

The 800Geth solutions provides backward compatibility with lower speed and optionally implements a BCH16K FEC stronger than the standard RS(544, 514) FEC which can be used to improve the Bit Error Rate (BER) for example when the PCS Core is used over noisy backplanes or to extend distances between equipments.

800Gbps Ethernet PCS

The 800Gbps Ethernet PCS Core implements the Reed-Solomon FEC (RS-FEC) of IEEE 802.3bs Clause 119 using RS(544/514) codewords or, optionally, a stronger BCH16K FEC.

The RS-FEC sublayer performs 257b transcoding and distributes data across 2x16 virtual FEC lanes which are bit-multiplexed to the Serdes lanes.

On receive it re-aligns the serial data stream to the RS/BCH16K FEC codeword boundaries performs deskew and lane re-mapping and performs RS / BCH16K FEC error correction and decode.

On the line side, the Core supports 16x53Gbps or 8x106Gbps Serdes interface options.

On the MAC side, the Core implements a 1024-Bit 800GMII (800G Media Independent Interface) with support for two standard 512-Bit CDMII then offering two independent channels of 200G or 400G interfaces.

Main Features

  • Aggregate 800G datastream using 32 virtual lanes multiplexing with 32 lanes deskew and reordering at receive
  • 1024-bit CDMII MAC Interface with backward compatibility with two standard 512-Bit CDMII 200/400Geth interfaces
  • Interleaved Reed-Solomon Forward Error Correction RS-FEC(544, 514)
  • Bit Error Rate improvement with BCH16K FEC option
  • Low Latency implementation with dedicated wide RS-FEC Datapath
  • Configurable FEC symbol error monitoring with High-Symbol error indication (Hi-SER)
  • Additional FEC symbol error monitoring with Degrade indication (Deg-SER)
  • Transport of degrade indications through marker block dedicated signaling bits
  • The RS-FEC error propagation to the PCS can be bypassed with software programming to reduce the Core latency.
  • Flexible Serdes interfaces configurable to implement 26.5625 or  53.125Gbps or 106.25Gbps interfaces
  • Control/Configuration/Status register access with 16-bit generic control interface.
  • Transmit and Receive data-path operating on a single Reference clock with a low minimum Frequency requirement of 800MHz

 

800Gbps Ethernet MAC

The MAC can be used in transport or Ethernet switching applications, passing received MAC frames without modification to the User application or to the Ethernet line. It provides support statistics for IEEE managed objects, IETF MIB-II and RMON for management applications (e.g. SNMP).

On the application side, the MAC Core implements a flexible FIFO / AXI4S interface that can be connected to a custom user application.

Main Features

  • Full MAC layer and Reconciliation sub-layer implementation compliant with IEEE 802.3bs specification
  • 1024bit application FIFO or AXI4S interface
  • Line side 512bit CDMII to 200G/400G PCS or 1024bit to 800G PCS
  • CRC-32 checking with optional forwarding of the FCS field to the user application
  • CRC-32 generation and append on transmit or forwarding of user application provided FCS selectable on a per-frame basis
  • Optional Ethernet Pause Frame (802.3 Annex 31A) termination providing fully automated flow control without any user application overhead
  • Optional Priority Flow Control (PFC) frame support allowing 8 or 16 classes for higher layer congestion management
  • Pause Frame generation by dedicated command pin with programmable Quanta
  • Programmable frame maximum length providing support for any frame up to 32K (e.g. Jumbo Frame or any tagged Frame)
  • Support for VLAN tagged frames according to IEEE 802.1Q
  • Basic and mandatory managed Objects statistics and IETF Management Information Database (MIB) package (RFC2665) and Remote Network Monitoring (RMON) counters
  • Optional internal statistics 64bit counters or statistics vector at toplevel for external statistics counting.
  • Clause 45 MDIO Master interface for PHY device configuration and management.
  • Support for IEEE 1588 applications providing frame timestamping.
  • Optional Timing Frame update module with automatic on-the-fly (1-step) correction field update for IEEE 1588 applications.