800G Ethernet IP
To complement MorethanIP proven and widely used 400Geth Cores and to meet Data Center increased demand for Bandwidth and for port density, MorethanIP has developed a complete 8-Lane 800Geth PCS and MAC Solution.
The 800Geth PCS and MAC are available as standalone Cores or integrated in MorethanIP 8-Lane multirate 10/25/50/100/200/400/800Geth Core.
MorethanIP 800Geth PCS and MAC solution is available, fully verified and has been adopted by multiple industry leaders for chip-to-chip connection and fiber interfaces.
The 800 Gigabit Ethernet Base-R PCS Core follows the 400G IEEE 802.3bs standard and is designed to be used in conjunction with the MorethanIP 800 Gigabit Ethernet MAC Core to create flexible system solutions.
On the line side, the PCS implements eight 96-, 128- or 160-Bit Serdes Lanes that can be connected to any industry standard 106.25Gbps or, for an increased bandwidth, faster Serdes.
The PCS implements the Reed Solomon RS(544,514) FEC structure compliant with IEEE802.3bs Clause 119 with RS-FEC codewords interleaving. The PCS RS-FEC is also optimized for low latency.
The PCS in 800Geth mode aligns and re-arranges swapped Serdes lanes and deskew over 32 Virtual Lanes (VLs).
The 800G PCS Core implements a 1024-Bit wide 800GMII (800Gbps Media Independent Interface) to MorethanIP or third party 800Geth MAC.
The 800Geth PCS Core can be configured to implement two independent 200G or 400G interfaces for flexible dynamic rate systems and backward compatibility with existing lower rate interfaces.
For efficient line monitoring and debug, the PCS implements multiple line status information and error counters accessible with a 16-Bit generic or APB control interface.
MorethanIP 800Geth MAC is developed from the MorethanIP 400Geth MAC and implements the same functions and features.
To support full 800Gbps Line operation with minimum size frames, the MAC implement Deficit Idle Counter (DIC) and marker insertion compensation functions.
For IEEE1588 applications the MAC support frame timestamping on Receive and Transmit. Optionally the MAC can support 1-Step update of IEEE 1588 or OAM Timing Frames.
On the Client interface, the MAC implements a 1024-Bit generic FIFO or AXI4S interface.
The Core implements counters for the IEEE managed objects, IETF MIB-II and RMON for management applications (e.g. SNMP).
For configuration register access and statistic gathering the MAC implements a 32-Bit generic or APB control interface.