In the continuous development of the IEEE for Ethernet lays the foundations for highly scalable and yet well defined networking infrastructures adopted by many industries. One of the major achievements is Ethernet’s scalability in supporting applications from low rate consumer and home environments to the highest performance telecom backbone and storage networks. This flexibility however calls for the system architect to choose the right compromise between integration complexity, application support, scalability, new standards support and, eventually, time and risk for product development.
MorethanIP provides Cores for each Ethernet speed from 10Mbps to 800Gbps and, with the Ethernet Hydra Core, multi-rate solutions that are field configurable to operate at any rate. The family of Multi-Channel Multi-Rate Hydra Cores is extensible and customizable with the following predefined solutions available addressing different interfaces and implementation tradeoffs:
- 4-Lane 10/40/100 Geth Hydra Core:
- 4-Lane 10/40/100/200 Geth Hydra Core
- 8-Lane 10/40/100/200/400 Geth Hydra Core
- 8-Lane 10/40/100/200/400/800 Geth Hydra Core
Using the Hydra Cores, companies can maximize important ASIC NRE costs and develop products for today, tomorrow and legacy markets. The Hydra Cores are available and silicon proven in different process nodes.
Low Latency Solutions
MorethanIP MAC and PCS IP optimized for latency and a specific low Ilatency RS-FEC solution
RS(272, 258), compliant with the 25/50Geth Consortium specification.
To meet to requirement of applications such as 5G Wireless Network MorethanIP PCS Cores can be optimized to provide sub-nanosecond Timestamping accuracy.
Complete Feature Set
- IEEE 802.3 1G to 400G speeds
- IEEE 1588
- IEEE 802.3az, Energy Efficient Ethernet (EEE)
- IEEE 802.1Qbb Priority-based Flow Control (PFC)
- Backplane Ethernet with Auto-Negotiation, Link Training and Forward Error Correction (FEC) options
- Ethernet in First Mile (EFM) and Custom Preamble
- Reed Solomon Forward Error Correction
- Fire Code Forward Error Correction
The Timestamping function is protocol independent and can then be used to implement precise time synchronization in, for example, IEEE 1588 Precision Time Protocol (PTP), IEEE 802.1as AVB (Audio Video Broadcast, AVB) or other timing protocols.
For a maximum precision, Timestamps are generated with low jitter to meet stringent Telecom application requirements.
All MAC Cores support 2-step applications whereas the Core generates to the system a timestamp for each timing frame. The system should then use the timestamp to generate and send a follow-up frame.
Also available for all MAC and for all Speeds, an optional module is also available for 1-step 1588 applications. The 1-Step module can be used to automatically update, on-the-fly, the timing fields in the outgoing frames.
As a 1588 network may use Timing information over Layer 2 Typed Frames, over UDP/IPv4 or over UDP/IPv6, the 1-Step module also performs automatic CRC and UDP checksum correction.
The 1-Step variant can be used to reduce application and network overhead.
MLG and FlexE Technologies
Support for OIF-FLEXE-01.0 flexible Ethernet (FlexE) using 100G link technology. Allows transport of multiple channels multiplexed over one or multiple links with dynamic bandwidth allocation and additional management capabilities. The MorethanIP FlexE Mux/Demux function supports operation over 1 to 5 links of 100G with management (calendar) transport and block multiplexing and seamless re-configuration.
The Multi-Link Gearbox (MLG) implements functions defined by the OIF Multi-link Gearbox Implementation Agreement (MLG IA). It leverages an IEEE 802.3 Clause 82 100G PCS and related PHY layers creating a transport layer for multiplexing up to 10 independent channels of 10G Ethernet (MLG1.0) or a combination of 10G and 40G Ethernet (MLG2.0) channels into a 100G Ethernet link. In addition (MLG3.0) use of RSFEC and an in-band remote management (RM) channel can be supported.
Technology Friendly Solutions
The Hydra Cores are designed for ease of use and ease of integration in large ASIC or FPGA devices.
The PMA line clocks, generated by the peripheral Serdes blocks, only drive a very small portion of the Core while the majority of the Core logic runs on a single clock domain (System Clock).
The system clock does not need to be changed when the Core mode of operation is switched, for example, from 100Geth to multiple 40Geth or to multiple 10Geth ports.
The system clock can also be generated from any free running oscillator and does not need to be frequency locked with any of the line or application clocks.
The Hydra solution therefore simplifies the chip level clock distribution and eliminates any clock muxing elements or PLLs that are typically used in multi-rate designs to create multiple frequency locked clocks with precise frequency.
These methods together, provide Cores that are easy to integrate and can be freely placed with any form factor.
Customer Specific Solutions
The standard Hydra Cores can be modified by modified by MorethanIP, for example, to change the number of Lanes or add different line interfaces. MorethanIP can also add customer specific features.