Time-Sensitive Networking (TSN) is a set of standards developed by the IEEE 802.1 Time-Sensitive Networking task group of the IEEE 802.1 working group. The standards define mechanisms for the time-sensitive transmission of data over Ethernet networks to address the transmission of very low transmission latency and high availability.
MorethanIP TSN solution includes a MAC Core that can be used in end-point applications and a Switch which both implement the essential elements of a TSN network:
- Time Synchronization with support for IEEE 1588 with Hardware timestamping and 1-step update support.
- Scheduling and Shaping with IEEE 802.3br traffic interspersing using frame preemption.
- Network Reliability Functions
The MorethanIP TSN Cores provide a complete solution for converged networks with real-time control streams required in automotive, telecommunication and industrial control applications.
1G to 100G Anyspeed TSN MAC
TSN MAC Features
- Full MAC layer and Reconciliation sub-layer implementation compliant with IEEE 802.3 specification for 1Gbps, 10Gbps, 25Gbps, 40Gbps, 50Gbps and 100Gbps Ethernet
- Support for 40 Gigabit and 50 Gigabit with a 64-bit XLGMII Interface. Can be configured to support 10 Gigabit / 25 Gigabit with a 64-bit XGMII Interface.
- Low Latency 64-bit data-path implementation for up to 50G operation.
- 128-Bit Transmit and Receive data-path for 100G operation
- EEE (Energy Efficient Ethernet) XLGMII and XGMII signaling according to the IEEE802.3bj and IEEE802.3az specifications
- Can be configured for NIC (Network Interface Card) applications or Switching / Bridging applications with options like CRC forwarding and promiscuous mode
- CRC-32 checking with optional forwarding of the FCS field to the user application.
- CRC-32 generation and append on transmit or forwarding of user application provided FCS selectable on a per-frame basis.
- Optional Ethernet Pause Frame (802.3 Annex 31A) termination providing fully automated flow control without any user application overhead
- Optional Priority Flow Control (PFC) frame support allowing 8 classes for higher layer congestion management. 16 classes supported via a synthesis parameter.
- Pause Frame generation by dedicated command pin with programmable Quanta
- Programmable frame maximum length providing support for any frame up to 32K (e.g. Jumbo Frame or any tagged Frame)
- Support for VLAN tagged frames according to IEEE 802.1Q and double VLAN Tags (Stacked VLANs)
- Clock and data rate decoupling with programmable asynchronous FIFOs
- Simple 256-Bit/128-bit/64-bit FIFO client application interface, configurable via synthesis option.
- Optional 802.3 basic and mandatory managed Objects statistic counters and IETF Management Information Database (MIB) package (RFC2665) and Remote Network Monitoring (RMON) counters
- Programmable Clause 22 and Clause 45 MDIO Master interface for PHY device configuration and management
- Support for IEEE1588 applications providing receive and transmit timestamps with additional transmit timestamp storage and interrupt, and 1-step frame update.
- Deficit Idle Counter (DIC) for optimized performance with minimum IPG. Support for non-standard short preambles.
- Short preamble support (4 bytes or 1 byte) via a synthesis option. User configurable preamble supported in normal 8 bytes preamble mode, also via a synthesis option.
- IEEE 802.3br traffic interspersing with frame preemption.
- Two classes traffic classification for AVB applications in the preemptable MAC.
Time Sensitive Networking Functions
- Hardware timestamping on line ports with 1-step update support.
- Enables implementing application specific control protocol software (802.1at: SRP, 1588/802.1as: PTP, etc.) by special forwarding rules for protocol frames to/from management port. Protocol software is not provided.
- End-to-End and Peer-to-Peer transparent clock support with automatic (1-step) correction field updating for event frames passing through the switch without CPU involvement.
- Detection and controlled forwarding allowing implementation (software) boundary as well as end node master and slave clock implementations.
- Optional internal timestamp timer with fine granular update capabilities under software control for smooth synchronization and syntonization or use of external timer possible.
- Output queues control and traffic shaping capabilities
- 1Qav – Credit based shaper; Provides stream based bandwidth control while minimizing burstness on outgoing streams.
- 1Qbv – Enhancements for Scheduled Traffic; Time controlled (cyclic) queue gating enabling time-slot based bandwidth control.
- Enhanced queue resource allocation configuration (e.g. depth) and control functions for automatic or application controlled queue flushing and frame discard.
- 1Qch – Cyclic Queueing and Forwarding (CQF); Enables cycle (time-slot) based store & forward for deterministic per-hop forwarding delay: Frames received in a time slot are queued and forwarded only in next time slot.
- 3br and 802.1Qbu – Support for preemptive MAC function; Higher priority queue can interrupt ongoing frames from lower priority queues for more deterministic forwarding delay.
- Network Reliability Functions
- Set of Leaky Bucket resources at input ports for port and stream based bandwidth monitoring and policing or backpressure decisions.
- Traffic identification and flexible monitoring bucket associations based on combinations of MAC destination address, source address, VLAN identifier (VID), frame type and possibly IP protocol type.
- 1Qci – Per-Stream Filtering and Policing: Support stream identification at Layer 2 (MAC/VID) (i.e. no support for optional IP and higher layer stream identification)
Base Switching Capabilities
- Integrated Ethernet Switch engine supporting 3 to 11 ports (synthesis option)
- Integrated 10/100/1000 MACs with flexible rate PHY interface for up to 1Gbps easing use with any PHY interface type (e.g. SMII, RMII, MII, GMII, RGMII) depending on application.
- Switching engine providing 2 to 5 Gbps non-blocking switching capacity with high-speed FPGA (~200MHz) and higher in ASIC environments.
- Very low store&forward latency of <1µs for 100Mbps ports independent from frame size.
- Implements hardware address learning/aging without software involvement and look-up for up to 8K MAC addresses (synthesis scaleable).
- Uses one single-port memory as frame buffer shared for all queues of all ports to allow for large on-chip frame storage.
- General purpose or AHB-Lite Slave 32-bit interface for control & statistics register access
- VLAN table for 32 VLANs
- VLAN manipulation functions on receive (VLAN insert) and transmit (VLAN removal/overwrite)
- QoS support with 8 Output Queues per Port (optionally reducible to 4 Queues)
- Priority Classification based on VLAN priorities as well as IPv4 TOS/IPv6 COS with programmable mapping.
- Standard Frame size support (1536) or extended frame sizes up to 1700 bytes or Jumbo frames up to 10Kbyte (depends on memory availability).
- Single Port memory implementation for large memories
- MAC per port statistics
- MAC optional support for half-duplex in 10/100Mbps
- Switch statistics for total frames processed/discarded
- Pin selectable managed or unmanaged mode of operation with self-initialization.
- Hardware allows for implementation of Rapid Spanning Tree Protocol (RSTP).
- Hardware allows for use of the switch in IEEE 1588 or related environments
- Integrated MACs with timestamping capabilities;
- Full automatic 1-step correction field updates on transmitted frames
- External or Internal timer used as time base for all timestamping
- Exclusive forwarding of BPDU frames to/from management port.
- Mirroring function to allow copying of frames to management port and others
- Flexible frame snooping function to allow copying of frames to management port
- Supports configurable VLAN switching (i.e. flooding) when MAC address lookup to be omitted
- Support Multicast, Broadcast with flooding control to avoid unnecessary duplication of frames
- Programmable Multicast destination port mask (within lookup table entries) to restrict frame duplication for individual multicast addresses.
- Optional receive pattern match function for executing tasks based on specific frame reception.
- Full automatic initialization of all hardware after reset. Basic switching operation (including learning) starts immediately without having to wait for processor boot.